Circuit explanation
of PLL initialization circuit

Sequence diagram of PLL initialization circuit
As for the following explanation, it is referring to above-mentioned circuit diagram and the sequence diagram.

Operation immediately after the turning on

The circuit which is composed of TR1 and C is preparatory to rather delay the operation beginning of the initialization circuit from the turning on.
This is to send the dividing ratio setting data after making the PLL circuit the stable operating state after the turning on.
After the turning on, with the capacitor (C) which is connected with the base of TR1, the base electric current doesn't flow and TR1 becomes the OFF condition. Therefore, the input of X1 becomes H and the output of X1 becomes the L. The multi-vibrator circuit which is composed of X4 and X5 has begun the operation from immediately the turning on.
Because the output of X1 is in the L condition, CL of FF(H) becomes the L and becomes the cleared condition. Therefore, the output H becomes the L condition and the output becomes the H condition.
Also, because the input of the underside of X3 is the L, the pulse signal which is made in X4 and X5 is blocked and doesn't appear in CK of FF(H).
Because the output H of FF(H) is the L, through X8, FF(ABCD) and FF(E) are in the reset condition and the output A, B, C, D and E become the L condition.
In the time, the electric charge stagnates in capacitor(C) and the electric current begins to flow through the base of TR1. When TR1 becomes the ON condition, the output of X1 becomes H and the cleared condition of FF(H) is canceled. The input of the underside of X3, too, becomes H simultaneously with it and the pulse signal which was made in X4 and X5 becomes accepted. In this condition, because the output is in the H condition, it becomes the condition which X2, too, can pass the pulse signal through.
The output reverses when the CK signal of FF(H) changes into the L from H. Because it is, the output H becomes the H condition and the output becomes the L condition when CK becomes the L from H with the first pulse after the output of X1 becomes the H condition.
This time becomes the start of the initialization operation.
When the output becomes the L, the gate of X2 is closed and the pulse signal doesn't appear in CK of FF(H). Because it is, until the power supply becomes OFF when FF(H) turns over once, the condition of the output doesn't change.

Clock generation circuit

It uses the two NAND gates of X4, X5 and it composes the multi-vibrator circuit.
It makes the clock frequency about 700 Hz. The initialization operation is the operation only immediately after turning on. Because to make so high-speed wasn't necessary, it made above-mentioned frequency. There is not a basis.

Clock counter

It counts 17 bits of the data for the reference frequency divider, 17 bits of the data for the comparison frequency divider and the LE. It uses FF(ABCD) and FF(E) as the counter.
Because it has become the 32-bit counter in case of being to be just as it is, it resets FF(ABCD) and FF(E) when the clock of the 19th bit is inputted by AND condition of the output B[21=2] and the output E[24=16]. It is to make count the 18 clocks at the 1 cycle including the LE signal that it makes the 19th bit.

Generation of the data for the divider

IC1 and IC2 are the IC for the selector. In this IC, there are 16 pieces of input and one piece of output and four pieces of control input for the output choice. With the condition of the input for the four controls, the one can be chosen from 16 pieces of the input.
This time, because the dividing ratio is the fixation, as for 16 pieces of the input, it is fixing H(+5V) or L(0V) on the print pattern beforehand.
IC1 is for the reference frequency divider and IC2 is for the comparison frequency divider.
It connects the output of FF(ABCD) with the input for the control and it makes output 16 pieces of the input in the order. The circuit this time sends out the data for the reference frequency divider first and makes send out the data for the comparison frequency divider next.
Both are using the output of FF(ABCD) for the counter for the selector control.

As for the actual selector input, it is as follows.
It makes the phase comparison frequency which was divided with each divider 2KHz.
 The reference frequency : 2 MHz The comparison frequency : 119.3 MHz

Because it is, each dividing ratio is as follows.
 The reference frequency dividing ratio : 1000 The comparison frequency dividing ratio : 59650

It becomes the following when showing at the bit string.
 The reference frequency dividing data : 0000001111101000 The comparison frequency dividing data : 1110100100000010

The data is sent out on the right from the left. The left end becomes the data of 215 and the right end becomes the data of 20.

Switching-over of the reference and the comparison cycle

It changes the reference frequency dividing data and the comparison frequency dividing data in FF(F).
FF(F) turns over because the FF(E) is reset behind the 18-bit count and the output of E changes into the L from H and the output F of FF(F) becomes H from the L.
The output F and of FF(F) connect each of Y1 and Y2.
When the output of FF(F) is H, the gate of Y1 (for the reference frequency dividing data) opens and the data of IC1 is output by the DATA terminal.
When the output F of FF(F) is H, the gate of Y2 (for the comparison frequency dividing data) opens and the data of IC2 is output by the DATA terminal.

Generation of the control data

After sending out the dividing ratio setting data of the 16 bits, it sends out the control bit.
The generation timing of the control bit is the time of the condition of E (the 17th pulse).
It decides the contents of the control bit in the condition of at this point.
In the first cycle, is in the H condition and the control bit on the DATA, too, becomes H. (The specification for the reference frequency divider)
FF(F) turns over when the output E of FF(E) becomes the L from H.
Because it is, in the next cycle, becomes the L condition and the control bit on the DATA, too, becomes the L. (The specification for the comparison frequency divider)

Generation of the LE pulse

After sending out the 17-bit data, it makes the LE (the load enable) signal the H condition. The dividing ratio data which was sent to the PLL through the DATA line by this signal is set in the programmable counter of the divider.
The generation timing of the LE is the time of the condition of AE.
It generates the twice for the reference frequency divider and the comparison frequency divider.

Stop of the initialization circuit

FF(G) turns over when sending out the LE signal for the comparison frequency divider (the time when the output F changed into the L from H), G becomes the H condition and becomes the L condition.
When becomes the L, the input of the upperside of X4 of the multi-vibrator circuit becomes the L and the multi-vibrator circuit stops the operation.
With this, CLOCK to the PLL, too, stops and after that, the extra data setting isn't done.
The condition of FF(G) doesn't change until the power supply becomes OFF.

The dividing ratio specification to the PLL is done by above operation.