;*****************************************************************************************
; Copyright © [4/01/2000] Scenix Semiconductor, Inc. All rights reserved.
;
; Scenix Semiconductor, Inc. assumes no responsibility or liability for
; the use of this [product, application, software, any of these products].
; Scenix Semiconductor conveys no license, implicitly or otherwise, under
; any intellectual property rights.
; Information contained in this publication regarding (e.g.: application,
; implementation) and the like is intended through suggestion only and may
; be superseded by updates. Scenix Semiconductor makes no representation
; or warranties with respect to the accuracy or use of these information,
; or infringement of patents arising from such use or otherwise.
;*****************************************************************************************
;
; Filename:
;		spis.src
;
; Authors:
;		Wing Poon, 3/24/00. 
;		(C) Scenix Semiconductor, Inc.
;
; Revision:	1.1
;
; Target Part(s):
;		SX18/20/28AC, Datecode AA9932AB
; 		SX48/52BD, Datecode AB0004AC
;
; Default Oscillator Frequency:
; 		50MHz
; Assemblers:
;		SXKey28L Version 1.09 for SX18/20/28AC
;		SXKey52 Version 1.19 for SX48/52BD
;		SASM Version 1.45.5
;	
; Date Written:
;		3/24/00
;
; Program Description:
;		This program is a 100kHz SPI Slave device. It emulates a 16byte EEPROM slave.
;		It has been tested on the SX28/52 Demoboard to interface to the 
;		master SPI VP on the same board. 
;		To run the demo, you should connect the interface pins described below
;		with the corresponding interface pins on the SPI Master VP (spim.src).
;		Please refer to the SPI documentation that can be found on the Scenix
;		web site for further information about the demo application. 
;
;
; Interface Pins:
;
; 		spisSdoPin	equ	rb.1	; Slave Data out pin
;		spisSdiPin	equ	rb.2	; Slave Data in pin
; 		spisSckPin	equ	rb.3	; Clock (input) pin
; 		spisCSPin	equ	rb.4	; Chip select pin (slave select)
;						
; Revision History:
;
;		1.00 	Initial version. Wing Poon 3/24/00. 
;		1.1	Rewritten according to "vp_guide_1_04.src". Corrected some bugs with
;			the CPHA and CPOL and made the assembler directives compatible with both
;			SASM and Parallax. The VP is now compliant with all the SPI modes.
;			The demo is changed and interacts with the SPI Master VP. JEE/OG 10/09/00
;
; Virtual Peripherals:
;
;		The included virtual peripherals are fully documented in the SPI document
;		describing the SPI Virtual Peripherals. The API is found in the header of
;		each of the subroutines/functions in this source code.
;*****************************************************************************************
; Target SX
; Uncomment one of the following lines to choose the SX18AC, SX20AC, SX28AC, 
; SX48BD, or SX52BD.
;*****************************************************************************************
;SX18_20
;SX28
SX48_52

;*****************************************************************************************
; Assembler Used
; Uncomment the following line if using the Parallax SX-Key assembler. SASM assembler
; enabled by default.
;*****************************************************************************************
;SX_Key

;*****************************************************************************************
; Runnable Demo?
; Uncomment the following line to enable the main program, creating a runnable demo
;*****************************************************************************************
;DEMO

	;*********************************************************************************
	; Assembler directives:
	;	high speed external osc, turbo mode, 8-level stack, and extended option reg.
	;
	;	SX18/20/28 - 4 pages of program memory and 8 banks of RAM enabled by default.
	;	SX48/52 - 8 pages of program memory and 16 banks of RAM enabled by default.
	;
	;*********************************************************************************

IFDEF SX_Key 				;SX-Key Directives
  IFDEF SX18_20				;SX18AC or SX20AC device directives for SX-Key
		device	SX18L,oschs2,turbo,stackx_optionx
  ENDIF
  IFDEF SX28				;SX28AC device directives for SX-Key		
		device	SX28L,oschs2,turbo,stackx_optionx
  ENDIF
  IFDEF SX48_52				;SX48/52/BD device directives for SX-Key
		device	oschs2
  ENDIF
		freq	50_000_000	; Debugger frequency

		watch	spisStatus,8,uhex
		watch	spisTxData,8,uhex
		watch	spisRxData,8,uhex
		watch	spisEdgeCount,8,uhex
		watch	spisPortPrev,8,uhex
		watch	spisTemp,8,uhex
		watch	spisTxBuf,8,uhex
		watch	spisAddr,16,uhex
		watch	spisRamBank,16,fstr
ELSE					;SASM Directives
  IFDEF SX18_20				;SX18AC or SX20AC device directives for SASM
		device	SX18,oschs2,turbo,stackx,optionx
  ENDIF
  IFDEF SX28				;SX28AC device directives for SASM
		device	SX28,oschs2,turbo,stackx,optionx
  ENDIF
  IFDEF SX48_52				;SX48BD or SX52BD device directives for SASM
		device	SX52,oschs2
  ENDIF
ENDIF
		id	'SPIS'
		reset	resetEntry	; set reset vector 

;*****************************************************************************************
; Macros
;*****************************************************************************************
	;?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?
	; Virtual Peripheral Guidelines Tip:
	;
	;	To support compatibility between source code written for the SX28 and the SX52,
	;	use macros.
	;
	;?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?

	;*********************************************************************************
	; Macro: _bank
	; Sets the bank appropriately for all revisions of SX.
	;
	; This is required since the bank instruction has only a 3-bit operand, it cannot
	; be used to access all 16 banks of the SX48/52. For this reason, FSR.7
	; (SX48/52bd production release) needs to be set appropriately, depending
	; on the bank address being accessed.
	;
	; So, instead of using the bank instruction to switch between banks, use _bank instead.
	; 
	;*********************************************************************************

_bank	macro	1
	bank	\1

	IFDEF SX48_52
	    IF \1 & %10000000		;SX48BD and SX52BD (production release) bank instruction 
		setb	fsr.7		;modifies FSR bits 4,5 and 6. FSR.7 needs to be set by software.
	    ELSE
		clrb	fsr.7
	    ENDIF
	ENDIF
	endm


	;*****************************************************************************************
	; Macros for SX28/52 Compatibility
	;*****************************************************************************************
	;*********************************************************************************
	; Macro: _mode
	; Sets the MODE register appropriately for all revisions of SX.
	;
	; This is required since the MODE (or MOV M,#) instruction has only a 4-bit operand. 
	; The SX18/20/28AC use only 4 bits of the MODE register, however the SX48/52BD have 
	; the added ability of reading or writing some of the MODE registers, and therefore use
	; 5-bits of the MODE register. The  MOV M,W instruction modifies all 8-bits of the 
	; MODE register, so this instruction must be used on the SX48/52BD to make sure the MODE
	; register is written with the correct value. This macro fixes this.
	;
	; So, instead of using the MODE or MOV M,# instructions to load the M register, use
	;  _mode instead.
	; 
	;*********************************************************************************
_mode	macro	1
	IFDEF SX48_52
  expand
		mov	w,#\1		;loads the M register correctly for the SX48BD and SX52BD
		mov	m,w
  noexpand
	ELSE
  expand
		mov	m,#\1		;loads the M register correctly for the SX18AC, SX20AC
  noexpand					;and SX28AC
	ENDIF
	endm

	;*****************************************************************************************
	; INCP/DECP macros for incrementing/decrementing pointers to RAM
	; used to compensate for incompatibilities between SX28 and SX52
	;*****************************************************************************************

	;?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?
	; Virtual Peripheral Guidelines Tip:
	;
	;   	To support compatibility between source code written for the SX28 and the SX52,
	;	use macros.  This macro compensates for the fact that RAM banks are contiguous in
	;	the SX52, but separated by 0x20 in the SX18/28.
	;
	;?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?

INCP	macro	1
		inc	\1
	IFNDEF	SX48_52
		setb	\1.4		; If SX18,20 or SX28, keep bit 4 of the pointer = 1
	ENDIF				; to jump from $1f to $30, etc.
endm
		
DECP	macro	1
	IFDEF	SX48_52
		dec	\1
	ELSE
		clrb	\1.4		; If SX18,20 or SX28, forces rollover to next bank
		dec	\1		; if it rolls over.  (Skips banks with bit 4 = 0)
		setb	\1.4		; Eg:  $30 --> $20 --> $1f --> $1f
	ENDIF				; AND: $31 --> $21 --> $20 --> $30
endm

	;*****************************************************************************************
	; Error generating macros
	; Used to generate an error message if the label is unintentionally moved into the 
	; second half of a page.  Use for lookup tables.
	;*****************************************************************************************

	;?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?
	; Virtual Peripheral Guidelines Tip:
	;
	;   	Surround lookup tables with the tableStart and tableEnd macros.  An error will
	;	be generated on assembly if part of the table is in the second half of a page.
	;	
	;	Example:
	;		lookupTable1
	;			add	pc,w	; Add w register to program counter
	;		tableStart
	;			retw	0
	;			retw	4
	;			retw	8
	;			retw	4
	;		tableEnd
	;
	;?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?

tableStart	macro 0			; Generates an error message if code that MUST be in
					; the first half of a page is moved into the second half.
	if $ & $100
		ERROR  'Must be located in the first half of a page.'
	endif
endm

tableEnd	macro 0			; Generates an error message if code that MUST be in
					; the first half of a page is moved into the second half.
	if $ & $100
		ERROR  'Must be located in the first half of a page.'
	endif
endm

;*****************************************************************************************
; Data Memory address definitions
; These definitions ensure the proper address is used for banks 0 - 7 for 2K SX devices
; (SX18/20/28) and 4K SX devices (SX48/52). 
;*****************************************************************************************
IFDEF SX48_52

global_org	=	$0A
bank0_org	=	$00
bank1_org	=	$10
bank2_org	=	$20
bank3_org	=	$30
bank4_org	=	$40
bank5_org	=	$50
bank6_org	=	$60
bank7_org	=	$70

ELSE

global_org	=	$08
bank0_org	=	$10
bank1_org	=	$30
bank2_org	=	$50
bank3_org	=	$70
bank4_org	=	$90
bank5_org	=	$B0
bank6_org	=	$D0
bank7_org	=	$F0

ENDIF
;*****************************************************************************************
; Global Register definitions
; NOTE: Global data memory starts at $0A on SX48/52 and $08 on SX18/20/28.
;*****************************************************************************************

		org	global_org

	;?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?
	; Virtual Peripheral Guidelines Tip:
	;
	;   	Use only these defined label types for global registers.  If an extra temporary 
	;	register is required, adhere to these label types.  For instance, if two temporary
	;	registers are required for the Interrupt Service Routine, use the labels isrTemp0
	;	and isrTemp1.
	;?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?

flags0		equ	global_org + 0  ; stores bit-wise operators like flags 
;VP_BEGIN: SPI Slave
	spisRxAvailable	equ	flags0.0; Indicates that a received byte is available
;VP_END: SPI Slave
					; and function-enabling bits (semaphores)
flags1		equ	global_org + 1  ; stores bit-wise operators like flags 
					; and function-enabling bits (semaphores)
localTemp0	equ	global_org + 2	; temporary storage register
					; Used by first level of nesting
					; Never guaranteed to maintain data
localTemp1	equ	global_org + 3	; temporary storage register	
					; Used by second level of nesting
					; or when a routine needs more than one 
					; temporary global register.	
localTemp2	equ	global_org + 4	; temporary storage register
					; Used by third level of nesting or by
					; main loop routines that need a loop 
					; counter, etc.
isrTemp0	equ	global_org + 5	; Interrupt Service Routine's temp register.  
					; Don't use this register in the mainline.

;*****************************************************************************************
; RAM Bank Register definitions
;*****************************************************************************************

	;*********************************************************************************
	; Bank 0
	;*********************************************************************************
		org     bank0_org
bank0		=	$

	;?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?
	; Virtual Peripheral Guidelines Tip:
	; 	- Avoid using bank0 in programs written for SX48/52.
	;?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?

	;*********************************************************************************
	; Bank 1
	;*********************************************************************************
		org     bank1_org
;VP_BEGIN: SPI Slave
spisBank	= 	$
spisTxData	ds	1	; byte to be transmitted
spisRxData	ds	1	; byte received
spisEdgeCount	ds	1	; (number of bits left to transmit/receive) x 2
spisPortPrev	ds	1	; previous state of SPI-Slave port
spisTemp	ds	1	; temporary storage used by SPI-Slave ISR
spisTxBuf	ds	1	; working register for buffering TX-byte
spisAddr	ds	2	; 16 bits address
;VP_END: SPI Slave

;VP_BEGIN: SPI Demo
spisStatus	ds	1	; slave status register
	spisStatWPEN	equ	spisStatus.7 ; WriteProtectEnable bit
	spisStatWEL	equ	spisStatus.1 ; WriteEnable bit
	spisStatWIP	equ	spisStatus.0 ; WriteInProgress bit
;VP_END: SPI Demo

	;?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?
	; Virtual Peripheral Guidelines Tip:
	;
	;	Tip 1:
	;	Indicate which Virtual Peripherals a portion of source code or declaration belongs
	;	to with a ;VP_BEGIN: VirtualPeripheralName and VP_END: comment.
	;
	;	Tip 2:
	;	All RAM location declaration names should be
	;   	- left justified
	;	- less than 2 tabs in length
	;	- written in hungarian notation
	;	- prefixed by a truncated version of the Virtual Peripheral's name
	;	
	;	Examples:
	;
	;	;VP_BEGIN: RS232 Transmit
	;	rs232TxBank	=       $	;UART Transmit bank
	;	rs232TxHigh	ds      1	;hi byte to transmit
	;	rs232TxLow	ds      1	;low byte to transmit
	;	rs232TxCount	ds      1	;number of bits sent
	;	rs232TxDivide	ds      1	;xmit timing (/16) counter
	;	;VP_END: RS232 Transmit
	;
	;?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?

;VP_BEGIN: VP Scheduler
isrMultiplex	ds	1	; The isrMultiplex register is used to switch to a new
;VP_END: VP Scheduler		; execution thread on each pass of the ISR.

	;*********************************************************************************
	; Bank 2
	;*********************************************************************************
		org	bank2_org
bank2		=	$
;VP_BEGIN: SPI Slave
spisRamBank	=	$
spisDataBuf	ds	16	; Reservation for EEPROM Demo application
;VP_END: SPI Slave

	;*********************************************************************************
	; Bank 3
	;*********************************************************************************
		org	bank3_org
bank3		=	$
	;*********************************************************************************
	; Bank 4
	;*********************************************************************************
		org	bank4_org
bank4		=	$
	;*********************************************************************************
	; Bank 5
	;*********************************************************************************
		org	bank5_org
bank5		=	$
	;*********************************************************************************
	; Bank 6
	;*********************************************************************************
		org	bank6_org
bank6		=	$
	;*********************************************************************************
	; Bank 7
	;*********************************************************************************
		org	bank7_org
bank7		=	$

IFDEF SX48_52
	;*********************************************************************************
	; Bank 8
	;*********************************************************************************
		org	$80	;bank 8 address on SX52
bank8		=	$
	;?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?
	; Virtual Peripheral Guidelines Tip:
	; 	- This extra memory is not available in the SX18/28, so don't use it for Virtual
	;	  Peripherals written for both platforms.
	;?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?
	;*********************************************************************************
	; Bank 9
	;*********************************************************************************
		org	$90	;bank 9 address on SX52
bank9		=	$
	;*********************************************************************************
	; Bank A
	;*********************************************************************************
		org	$A0	;bank A address on SX52
bankA		=	$
	;*********************************************************************************
	; Bank B
	;*********************************************************************************
		org	$B0	;bank B address on SX52
bankB		=	$
	;*********************************************************************************
	; Bank C
	;*********************************************************************************
		org	$C0	;bank C address on SX52
bankC		=	$
	;*********************************************************************************
	; Bank D
	;*********************************************************************************
		org	$D0	;bank D address on SX52
bankD		=	$
	;*********************************************************************************
	; Bank E
	;*********************************************************************************
		org	$E0	;bank E address on SX52
bankE		=	$
	;*********************************************************************************
	; Bank F
	;*********************************************************************************
		org	$F0	;bank F address on SX52
bankF		=	$
ENDIF
	;*********************************************************************************
	; Pin Definitions:
	;*********************************************************************************

	;?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?
	; Virtual Peripheral Guidelines Tip:
	; 	- Store all initialization constants for the I/O in the same area, so
	;	  pins can be easily moved around.
	;	- Pin definitions should follow the same format guidelines as RAM definitions
	;		- Left justified
	;		- No underscores.  Indicate word separation with capital letters
	;		- Less that 2 tabs in length
	;		- Indicate the Virtual Peripheral the pin is used for
	;		- All pin definitions for a specific VP must have the same prefix
	;	- Only use symbolic names to access a pin/port in the source code.
	;	- Example:
	;		; VP_BEGIN: RS232 Transmit
	;			rs232TxPin	equ	ra.3
	;		; VP_END: RS232 Transmit
	;?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?

RA_latch	equ	%00000000		;SX18/20/28/48/52 port A latch init
RA_DDIR		equ	%11111111		;SX18/20/28/48/52 port A DDIR value
RA_LVL		equ	%00000000		;SX18/20/28/48/52 port A LVL value
RA_PLP		equ	%11111111		;SX18/20/28/48/52 port A PLP value

RB_latch	equ	%00000000		;SX18/20/28/48/52 port B latch init
RB_DDIR		equ	%11111101		;SX18/20/28/48/52 port B DDIR value
RB_ST		equ	%11111111		;SX18/20/28/48/52 port B ST value
RB_LVL		equ	%00000000		;SX18/20/28/48/52 port B LVL value
RB_PLP		equ	%11111111		;SX18/20/28/48/52 port B PLP value

;VP_BEGIN: SPI Slave
spisPort	equ	rb
spisSdo		equ	1
spisSdi		equ	2
spisSck		equ	3
spisCS		equ	4
spisSdoPin	equ    	spisPort.spisSdo	; Slave Data out pin
spisSdiPin	equ    	spisPort.spisSdi	; Slave Data in pin
spisSckPin	equ	spisPort.spisSck	; Clock (input) pin
spisCSPin	equ	spisPort.spisCS		; Chip select pin (slave select)
;VP_END: SPI Slave


IFNDEF	SX18_20	; There is no C port on SX18/20

;VP_BEGIN: SPI Demo
spisOutPort	equ	rc			; Demo Output for slave
;VP_END: SPI Demo

RC_latch	equ	%00000000		;SX18/20/28/48/52 port C latch init
RC_DDIR		equ	%00000000		;SX18/20/28/48/52 port C DDIR value
RC_ST		equ	%11111111		;SX18/20/28/48/52 port C ST value
RC_LVL		equ	%00000000		;SX18/20/28/48/52 port C LVL value
RC_PLP		equ	%11111111		;SX18/20/28/48/52 port C PLP value

IFDEF SX48_52	;SX48BD/52BD Port initialization values
RD_latch	equ	%00000000		;SX48/52 port D latch init
RD_DDIR		equ	%11111111		;SX48/52 port D DDIR value
RD_ST		equ	%11111111		;SX48/52 port D ST value
RD_LVL		equ	%00000000		;SX48/52 port D LVL value
RD_PLP		equ	%11111111		;SX48/52 port D PLP value

RE_latch	equ	%00000000		;SX48/52 port E latch init
RE_DDIR		equ	%11111111		;SX48/52 port E DDIR value
RE_ST		equ	%11111111		;SX48/52 port E ST value
RE_LVL		equ	%00000000		;SX48/52 port E LVL value
RE_PLP		equ	%11111111		;SX48/52 port E PLP value
ENDIF	;(SX18_20)
ENDIF	;(SX48_52)

;*****************************************************************************************
; Program constants
;*****************************************************************************************

	;?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?
	; Virtual Peripheral Guidelines Tip:
	;	To calculate the interrupt period in cycles:
	;	- First, choose the desired interrupt frequency
	;		- Should be a multiple of each Virtual Peripherals sampling frequency.
	;		- Example:  19200kHz UART sampling rate * 16 = 307.200kHz
	;	- Next, choose the desired oscillator frequency.
	;		- 50MHz, for example.
	;	- Next calculate the 
	;	- Perform the calculation intPeriod = (cyclesPerSecond / interruptFrequency)
	;				  		= (50MHz / 307.2kHz)
	;						= 162.7604
	;	- Round intPeriod to the nearest integer:
	;						= 163
	;	- Now calculate your actual interrupt rate:
	;						= cyclesPerSecond / intPeriod
	;						= 50MHz / 163
	;						= 306.748kHz
	;	- This interrupt frequency will be the timebase for all of the Virtual 
	;	  Peripherals
	;?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?


intPeriod	=	50	; Gives an ISR rate of 50MHz/50 = 1MHz
				; SPI rate = 1/4 of ISR rate = 250kHz
				; The SPI rate should be MORE than twice the SPI bus clock frequency.

	;?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?
	; Virtual Peripheral Guidelines Tip:
	;	- Include all calculations for Virtual Peripheral constants for any sample 
	;	  rate.
	;	- Relate all Virtual Peripheral constants to the sample rate of the Virtual
	;	  Peripheral.
	;	- Example:
	;		; VP_BEGIN: 5ms Timer
	;		TIMER_DIV_CONST	equ 192	; This constant = timer sample rate/200Hz = 192
	;		; VP_END: 5ms Timer
	;
	;?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?

;VP_BEGIN: SPI Slave

;SPIM_CPHA1	; clock-phase: Uncomment this line if you want to set the CPHA=1
		; 1 = outputs data on first edge, while 0 = sample data on first edge after idle

;SPIM_CPOL1	; clock-polarity: Uncomment this line if you want to set CPOL=1
		; 0 = spimSck idle low, 1 = spisSck idle high


SPIM_TRANSITION		equ	16	; (number of bits to transmit/receive) x 2 
SPIM_VALID_CMD		equ	%11111000 ; Mask incomming command. Check that only the 3 LSb are used.
SPIM_RANGE		equ	%11110000 ; Address mask/range of slave. Set the used bits to zero.
					; I.e. if only 8 bytes is used, only set the 3 LSb to zero.
;VP_END: SPI Slave



;-------------------------------------------------------------------------------------
IFDEF SX48_52
	;*********************************************************************************
	; SX48BD/52BD Mode addresses
	; *On SX48BD/52BD, most registers addressed via mode are read and write, with the
	; exception of CMP and WKPND which do an exchange with W.
	;*********************************************************************************
; Timer (read) addresses
TCPL_R		equ	$00		;Read Timer Capture register low byte
TCPH_R		equ	$01		;Read Timer Capture register high byte
TR2CML_R	equ	$02		;Read Timer R2 low byte
TR2CMH_R	equ	$03		;Read Timer R2 high byte
TR1CML_R	equ	$04		;Read Timer R1 low byte
TR1CMH_R	equ	$05		;Read Timer R1 high byte
TCNTB_R		equ	$06		;Read Timer control register B
TCNTA_R		equ	$07		;Read Timer control register A

; Exchange addresses
CMP		equ	$08		;Exchange Comparator enable/status register with W
WKPND		equ	$09		;Exchange MIWU/RB Interrupts pending with W

; Port setup (read) addresses
WKED_R		equ	$0A		;Read MIWU/RB Interrupt edge setup, 0 = falling, 1 = rising
WKEN_R		equ	$0B		;Read MIWU/RB Interrupt edge setup, 0 = enabled, 1 = disabled
ST_R		equ	$0C		;Read Port Schmitt Trigger setup, 0 = enabled, 1 = disabled
LVL_R		equ	$0D		;Read Port Level setup, 0 = CMOS, 1 = TTL
PLP_R		equ	$0E		;Read Port Weak Pullup setup, 0 = enabled, 1 = disabled
DDIR_R		equ	$0F		;Read Port Direction

; Timer (write) addresses
TR2CML_W	equ	$12		;Write Timer R2 low byte
TR2CMH_W	equ	$13		;Write Timer R2 high byte
TR1CML_W	equ	$14		;Write Timer R1 low byte
TR1CMH_W	equ	$15 		;Write Timer R1 high byte
TCNTB_W		equ	$16		;Write Timer control register B
TCNTA_W		equ	$17		;Write Timer control register A

; Port setup (write) addresses
WKED_W		equ	$1A		;Write MIWU/RB Interrupt edge setup, 0 = falling, 1 = rising
WKEN_W		equ	$1B		;Write MIWU/RB Interrupt edge setup, 0 = enabled, 1 = disabled
ST_W		equ	$1C		;Write Port Schmitt Trigger setup, 0 = enabled, 1 = disabled
LVL_W		equ	$1D		;Write Port Level setup, 0 = CMOS, 1 = TTL
PLP_W		equ	$1E		;Write Port Weak Pullup setup, 0 = enabled, 1 = disabled
DDIR_W		equ	$1F		;Write Port Direction

ELSE

	;*********************************************************************************
	; SX18AC/20AC/28AC Mode addresses
	; *On SX18/20/28, all registers addressed via mode are write only, with the exception of
	; CMP and WKPND which do an exchange with W.
	;*********************************************************************************
; Exchange addresses
CMP		equ	$08		;Exchange Comparator enable/status register with W
WKPND		equ	$09		;Exchange MIWU/RB Interrupts pending with W

; Port setup (read) addresses
WKED_W		equ	$0A		;Write MIWU/RB Interrupt edge setup, 0 = falling, 1 = rising
WKEN_W		equ	$0B		;Write MIWU/RB Interrupt edge setup, 0 = enabled, 1 = disabled
ST_W		equ	$0C		;Write Port Schmitt Trigger setup, 0 = enabled, 1 = disabled
LVL_W		equ	$0D		;Write Port Schmitt Trigger setup, 0 = enabled, 1 = disabled
PLP_W		equ	$0E		;Write Port Schmitt Trigger setup, 0 = enabled, 1 = disabled
DDIR_W		equ	$0F		;Write Port Direction

ENDIF	;(SX48_52)


;*****************************************************************************************
; Program memory ORG defines
;*****************************************************************************************

	;?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?
	; Virtual Peripheral Guidelines Tip:
	; 	- Place a table at the top of the source with the starting addresses of all of
	;	  the components of the program.
	;?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?

INTERRUPT_ORG		equ	$0	; Interrupt must always start at location zero
RESET_ENTRY_ORG		equ	$1FB	; The program will jump here on reset.
SUBROUTINES_ORG		equ	$200	; The subroutines are in this location
STRINGS_ORG		equ	$300	; The strings are in location $300
PAGE3_ORG		equ	$400	; Page 3 is empty
MAIN_PROGRAM_ORG	equ	$600	; The main program is in the last page of program memory.













;****************************** Beginning of program space *******************************
	org	INTERRUPT_ORG			; First location in program memory.
;*****************************************************************************************
;------------------------------------------------------------------------------
; Interrupt Service Routine
;------------------------------------------------------------------------------
; Note: The interrupt code must always originate at address $0.
;
; Interrupt Frequency = OSC Frequency / ((-retiw value)*RTCC Prescaler)  For example:
; With a retiw value of -163, a prescaler of 1, and an oscillator frequency of 50MHz,
; this Interrupt Routine runs every 3.26us.
;------------------------------------------------------------------------------
ISR					;3	The interrupt service routine...

;------------------------------------------------------------------------------
;VP_BEGIN: VP Scheduler

	;?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?
	; Virtual Peripheral Guidelines Tip:
	; - Schedule tasks in the Interrupt Service Routine
	;	- Produces a FAR smaller worst-case cycle time count, and enables a larger number
	;	  of VP's to run simultaneously.  Also produces "empty" slots that future VP's 
	;	  can be copied and pasted into easily.
	;	- Determine how often your tasks need to run.  (9600bps UART can run well at a 
	;	  sampling rate of only 38400Hz, so don't run it faster than this.)
	;	- Strategically place each "module" into the threads of the Scheduler.  If a 
	;	  module must be run more often, just call it's module at double the rate or
	;	  quadruple the rate, etc.…
	;	- Split complicated Virtual Peripherals into several modules, keeping the 
	;	  high-speed portions of the Virtual Peripherals as small and quick as possible, 
	;	  and run the more complicated, slower processing part of the Virtual Peripheral 
	;	  at a lower rate.
	;?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?
	;------------------------------------------------------------------------------
	; Virtual Peripheral Scheduler:  up to 16 individual threads, each running at
	;				   the interrupt rate/16.  Change the table
	;				   to modify the rate at which each of the threads
	;				   is run.
	;
	;	Input variable(s): 		isrMultiplex: variable used to choose threads
	;	Output variable(s): 		None, executes the next thread
	;	Variable(s) affected: 		isrMultiplex
	;	Flag(s) affected: 		None
	;	Program Cycles:			10 cycles (turbo mode SX52)
	;------------------------------------------------------------------------------
	_bank	isrMultiplex		;2
	inc	isrMultiplex		;1		; toggle interrupt rates
	mov	w,isrMultiplex		;1
; The code between the tableBegin and tableEnd statements MUST be 
; completely within the first half of a page.  The routines 
; it is jumping to must be in the same page as this table.
tableStart				; Start all tables with this macro.
	add	pc,w			;3
	jmp	isrThread1		;3,9/10. 12/13 + 9/27 + 7 = 28/47cycles
	jmp	isrThread2		;
	jmp	isrThread3		;
	jmp	isrThread4		;
	jmp	isrThread1		; Call this thread 4 times/cycle for an execution rate of ISR_rate/4
	jmp	isrThread5		;
	jmp	isrThread6		;
	jmp	isrThread7		;
	jmp	isrThread1		;
	jmp	isrThread8		;
	jmp	isrThread9		;
	jmp	isrThread10		;
	jmp	isrThread1		;
	jmp	isrThread11		;
	jmp	isrThread12		;
	jmp	isrThread13		;
tableEnd				; End all tables with this macro.
;VP_END: VP Scheduler

;------------------------------------------------------------------------------
;VP_BEGIN: VP Scheduler
; ISR TASKS
;------------------------------------------------------------------------------
isrThread1		; Serviced at ISR rate / 4
;------------------------------------------------------------------------------
	;?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?
	; Virtual Peripheral Guidelines Tip:
	; 	The sample rate of this section of code is the isr rate / 4, because it is jumped
	;	to in every 4th entry in the VP Schedulers table.  To increase the
	;	sample rate, put more calls to this thread in the Scheduler's jump table.
	;?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?

;VP_BEGIN: SPI Slave
		_bank	spisBank		;1/2
		mov	w, spisPort		;1 ; read SPI port
		mov	spisTemp, w		;1 
		xor	w, spisPortPrev		;1 ; compare with previous state of port
		and	w, #(1 << spisSck)	;1
		snb	z			;1,6/7
		jmp	:spisExit		;3,9/10 ; no clk-edge detected

		mov	w,spisTemp		;1
		mov	spisPortPrev,w		;1 ; Store current state to "next previous"
IFDEF SPIM_CPHA1
		snb	spisEdgeCount.0		;1 ; when CPHA=1, start with dataOutEdge on first clk edge
		jmp	:dataInEdge		;3,13/14
ELSE
		sb	spisEdgeCount.0		;1 ; when CPHA=0, start with dataInEdge on first clk edge
		jmp	:dataInEdge		;3,13/14
ENDIF

:dataOutEdge		; Move bit to transmitt to SdoPin:
		sb	spisTxBuf.7		;1,12/13 ; 
		clrb	spisSdoPin		;1
		snb	spisTxBuf.7		;1 
		setb	spisSdoPin		;1

		rl	spisTxBuf		;1,16/17 ; Prepare next bit to transfer
		jmp	:spisDone		;3,19/20 ; When last bit is sent

:dataInEdge	rl	spisRxData		;1,14/15 ; Shift RxData before receiving

		clrb	spisRxData.0		;1 ; Move bit from Sdi to RxData(0)
		snb	spisPortPrev.spisSdi	;1
		setb	spisRxData.0		;1,17/18

:spisDone	decsz	spisEdgeCount		;1 ; Is this the last bit to receive?
		jmp	:spisExit		;3,21/24

		setb	spisRxAvailable		;1 ; Prepare for next byte to transmitt
		mov	w,#SPIM_TRANSITION	;1 ; For faster run time this part could 
		mov	spisEdgeCount,w		;1 ; be moved to the main program (-4 cycles).
		mov	w, spisTxData		;1
		mov	spisTxBuf,w		;1,24/27

:spisExit					;9/27
;VP_END: SPI Slave


	jmp	isrOut			;7 cycles until mainline program resumes execution

;------------------------------------------------------------------------------
isrThread2		; Serviced at ISR rate / 16
;------------------------------------------------------------------------------
	jmp	isrOut			;7 cycles until mainline program resumes execution

;------------------------------------------------------------------------------
isrThread3		; Serviced at ISR rate / 16
;------------------------------------------------------------------------------
	jmp	isrOut			;7 cycles until mainline program resumes execution

;------------------------------------------------------------------------------
isrThread4		; Serviced at ISR rate / 16
;------------------------------------------------------------------------------
	jmp	isrOut			;7 cycles until mainline program resumes execution

;------------------------------------------------------------------------------
isrThread5		; Serviced at ISR rate / 16
;------------------------------------------------------------------------------
	jmp	isrOut			;7 cycles until mainline program resumes execution

;------------------------------------------------------------------------------
isrThread6		; Serviced at ISR rate / 16
;------------------------------------------------------------------------------
	jmp	isrOut			;7 cycles until mainline program resumes execution

;------------------------------------------------------------------------------
isrThread7		; Serviced at ISR rate / 16
;------------------------------------------------------------------------------
	jmp	isrOut			;7 cycles until mainline program resumes execution

;------------------------------------------------------------------------------
isrThread8		; Serviced at ISR rate / 16
;------------------------------------------------------------------------------
	jmp	isrOut			;7 cycles until mainline program resumes execution

;------------------------------------------------------------------------------
isrThread9		; Serviced at ISR rate / 16
;------------------------------------------------------------------------------
	jmp	isrOut			;7 cycles until mainline program resumes execution

;------------------------------------------------------------------------------
isrThread10		; Serviced at ISR rate / 16
;------------------------------------------------------------------------------
	jmp	isrOut			;7 cycles until mainline program resumes execution

;------------------------------------------------------------------------------
isrThread11		; Serviced at ISR rate / 16
;------------------------------------------------------------------------------
	jmp	isrOut			;7 cycles until mainline program resumes execution

;------------------------------------------------------------------------------
isrThread12		; Serviced at ISR rate / 16
;------------------------------------------------------------------------------
	jmp	isrOut			;7 cycles until mainline program resumes execution

;------------------------------------------------------------------------------
isrThread13		; Serviced at ISR rate / 16
;------------------------------------------------------------------------------
	;?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?
	; Virtual Peripheral Guidelines Tip:
	; 	The final thread in the ISR Multi-Threader must load the isrMultiplex 
	; 	register with a value of 255, so it will roll-over to 0 on the next ISR.
	;?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?
	_bank	isrMultiplex
	mov	w,#255			; Reload isrMultiplex so isrThread1 will be run
	mov	isrMultiplex,w		; on next interrupt.

	jmp	isrOut
;VP_END: VP Scheduler
;------------------------------------------------------------------------------

;------------------------------------------------------------------------------
isrOut
;------------------------------------------------------------------------------
	mov	w,#-intPeriod	;1	; return and add -intPeriod to the RTCC
	retiw			;3	; using the retiw instruction.

;------------------------------------------------------------------------------










;*****************************************************************************************
org	RESET_ENTRY_ORG
;*****************************************************************************************
	;?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?
	; Virtual Peripheral Guidelines Tip:
	;	The main program operation should be easy to find, so place it at the end of the 
	;	program code.  This means that if the first page is used for anything other than 
	;	main program source code, a resetEntry must be placed in the first page, along 
	;	with a 'page' instruction and a 'jump' instruction to the beginning of the 
	;	main program, wherever that may be.
	;?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?
;------------------------------------------------------------------------------
resetEntry					; Program starts here on power-up
	page	_resetEntry
	jmp	_resetEntry
;------------------------------------------------------------------------------







	;?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?
	; Virtual Peripheral Guidelines Tip:
	;	ORG statements should use predefined labels rather than literal values.
	;?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?
org	SUBROUTINES_ORG

;*****************************************************************************************
; Subroutines
;*****************************************************************************************
;VP_BEGIN: SPI Slave
;------------------------------------------------------------------------------
spisInit
;	Description:
; 		SPI-Slave specific initialization code. Reads a 16byte demo-string 
;		from program memory (_demoString) to RAM-bank. 
;	Global Ram Destroyed:
;		None
;	Inputs:	16 bytes from _demoString
;	Output:	spisRamBank is filled with data from the _demoString
;------------------------------------------------------------------------------
		_bank	spisBank
		mov	w,#SPIM_TRANSITION 
		mov	spisEdgeCount,w
		clrb	spisRxAvailable
		clr	spisTxData
IFDEF SPIM_CPOL1
		setb	spisPortPrev.spisSck
ELSE
		clrb	spisPortPrev.spisSck
ENDIF

:loop		_mode	STRINGS_ORG>>8	   	; String base src address
		mov	w,#_demoString	   	; String offset address
		add	w,localTemp0	   
		iread		      	   	; Read Program memory
		or	w,#$00	      	   	
		snb	z
		jmp	:out			; String is 0 terminated
		
		mov	localTemp1,w	   	; Save string char temporary
		mov	w,#spisRamBank
		add	w,localTemp0	   	; String offset address
		mov	fsr,w
		mov	w,localTemp1	   
		mov	indf,w		   	; Write char to RAM
		inc	localTemp0	   	; Increment string offset counter
		sb	dc			; don't exceed 16 bytes in RAM-bank
		jmp	:loop
:out		retp


;------------------------------------------------------------------------------
spisGetByte
;	Description:
; 		Checks if received byte is available. If it is not it waits
;		until it is available and then returns the byte received in the
;		ISR in the work register.
;	Global Ram Destroyed:
;		None
;	Inputs:	none
;	Output:	w = received byte
;------------------------------------------------------------------------------
		_bank	spisBank
:wait		sb	spisRxAvailable
		jmp	:wait
		clrb	spisRxAvailable
		mov	w, spisRxData
		retp

;------------------------------------------------------------------------------
spisCheckRxByte
;	Description:
; 		Checks if received byte is available.
;	Global Ram Destroyed:
;		None
;	Inputs:	none
;	Output:	w: 1 = byte available, 0 = byte not available
;------------------------------------------------------------------------------
		_bank	spisBank
		clr	w
		snb	spisRxAvailable
		or	w, #1
		retp

;------------------------------------------------------------------------------
spisSetTxByte
;	Description:
; 		Transfers the next byte to transmitt to spisTxData. When the 
;		ISR is done transmitting the current byte,  spisTxData will be
;		moved to the spisTxBuf for transmitting on next run on the ISR.
;	Global Ram Destroyed:
;		None
;	Inputs:	w = byte to transmit
;	Output:	spisTxData
;------------------------------------------------------------------------------
		_bank	spisBank
		mov	spisTxData, w
		retp

;------------------------------------------------------------------------------
spisTxByte
;	Description:
; 		Moves the contents of wreg into TX-buffer. When doing this you 
;		must take care and not overwrite the byte that is currently 
;		beeing written. Make sure that the "spisRxAvailable" is set
; 		before entering.
;	Global Ram Destroyed:
;		None
;	Inputs:	w = byte to transmit
;	Output:	spisTxBuf (spisSdoPin if CPHA=0)
;------------------------------------------------------------------------------
		_bank	spisTxBuf
		mov	spisTxBuf,w

IFNDEF SPIM_CPHA1
		sb	spisTxBuf.7
		clrb	spisSdoPin
		snb	spisTxBuf.7
		setb	spisSdoPin
		rl	spisTxBuf
ENDIF
		retp
;VP_END: SPI Slave

;*****************************************************************************************
org	STRINGS_ORG		; This label defines where strings are kept in program space.
;*****************************************************************************************
;------------------------------------------------------------------------------
; Put String Data Here
;------------------------------------------------------------------------------

; Example:
;_hello          dw      13,10,'UART Demo',0

;VP_BEGIN: SPI Slave
_demoString	dw	'!! Erase me !! ',0 ; Maximum length is 16chars with current implementation
;VP_END: SPI Slave

	;?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?
	; Virtual Peripheral Guidelines Tip:
	; 	- Routines that use location-dependant data, such as in example below, should
	;	  use a LABEL rather than a literal value as their input.  Example:
	;	  instead of
	;		mov     m,#3		 ; move upper nybble of address of strings into m
	;	  use
	;		mov	m,#STRINGS_ORG>>8; move upper nybble of address of strings into m
	;?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?



;*****************************************************************************************
org	PAGE3_ORG
;*****************************************************************************************
	;?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?
	; Virtual Peripheral Guidelines Tip:
	;	To ensure that several Virtual Peripherals, when pasted together, do not cross 
	;	a page boundary without the integrator's knowledge, put an ORG statement and one 
	;	instruction at every page boundary.  This will generate an error if a pasted 
	;	subroutine moves another subroutine to a page boundary.  
	;?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?

	jmp	$	; This instruction will cause an assembler error if the source code before
			; the org statement inadvertantly crosses a page boundary.












;*****************************************************************************************
org	MAIN_PROGRAM_ORG
;*****************************************************************************************



;------------------------------------------------------------------------------
; RESET VECTOR 
;------------------------------------------------------------------------------

	;------------------------------------------------------------------------------
	; Program execution begins here on power-up or after a reset
	;------------------------------------------------------------------------------

_resetEntry
	;------------------------------------------------------------------------------
	; Initialize all port configuration
	;------------------------------------------------------------------------------

		_mode	ST_W			;point MODE to write ST register
		mov     w,#RB_ST            	;Setup RB Schmitt Trigger, 0 = enabled, 1 = disabled
		mov	!rb,w		
IFNDEF 	SX18_20
		mov     w,#RC_ST            	;Setup RC Schmitt Trigger, 0 = enabled, 1 = disabled
		mov	!rc,w	
ENDIF 	;(SX18_20)
IFDEF 	SX48_52
		mov     w,#RD_ST            	;Setup RD Schmitt Trigger, 0 = enabled, 1 = disabled
		mov	!rd,w		
		mov     w,#RE_ST            	;Setup RE Schmitt Trigger, 0 = enabled, 1 = disabled
		mov	!re,w		
ENDIF 	;(SX48_52)
		_mode	LVL_W			;point MODE to write LVL register
		mov     w,#RA_LVL            	;Setup RA CMOS or TTL levels, 0 = TTL, 1 = CMOS
		mov	!ra,w		 
		mov     w,#RB_LVL            	;Setup RB CMOS or TTL levels, 0 = TTL, 1 = CMOS
		mov	!rb,w		
IFNDEF 	SX18_20
		mov     w,#RC_LVL            	;Setup RC CMOS or TTL levels, 0 = TTL, 1 = CMOS
		mov	!rc,w	
ENDIF 	;(SX18_20)
IFDEF 	SX48_52
		mov     w,#RD_LVL            	;Setup RD CMOS or TTL levels, 0 = TTL, 1 = CMOS
		mov	!rd,w		
		mov     w,#RE_LVL            	;Setup RE CMOS or TTL levels, 0 = TTL, 1 = CMOS
		mov	!re,w		
ENDIF	;(SX48_52)
		_mode	PLP_W			;point MODE to write PLP register
		mov     w,#RA_PLP            	;Setup RA Weak Pull-up, 0 = enabled, 1 = disabled
		mov	!ra,w		 
		mov     w,#RB_PLP            	;Setup RB Weak Pull-up, 0 = enabled, 1 = disabled
		mov	!rb,w		
IFNDEF 	SX18_20
		mov     w,#RC_PLP            	;Setup RC Weak Pull-up, 0 = enabled, 1 = disabled
		mov	!rc,w	
ENDIF	;(SX18_20)
IFDEF 	SX48_52
		mov     w,#RD_PLP            	;Setup RD Weak Pull-up, 0 = enabled, 1 = disabled
		mov	!rd,w		
		mov     w,#RE_PLP            	;Setup RE Weak Pull-up, 0 = enabled, 1 = disabled
		mov	!re,w		
ENDIF	;(SX48_52)
		_mode	DDIR_W			;point MODE to write DDIR register
		mov	w,#RA_DDIR		;Setup RA Direction register, 0 = output, 1 = input		
		mov	!ra,w	
		mov	w,#RB_DDIR		;Setup RB Direction register, 0 = output, 1 = input
		mov	!rb,w			
IFNDEF 	SX18_20
		mov	w,#RC_DDIR		;Setup RC Direction register, 0 = output, 1 = input
		mov	!rc,w			
ENDIF	;(SX18_20)
IFDEF SX48_52
		mov	w,#RD_DDIR		;Setup RD Direction register, 0 = output, 1 = input
		mov	!rd,w			
		mov	w,#RE_DDIR		;Setup RE Direction register, 0 = output, 1 = input
		mov	!re,w			
ENDIF	;(SX48_52)
		mov     w,#RA_latch          	;Initialize RA data latch
		mov     ra,w		
		mov     w,#RB_latch         	;Initialize RB data latch
		mov     rb,w		
IFNDEF 	SX18_20
		mov     w,#RC_latch          	;Initialize RC data latch
		mov     rc,w		
ENDIF	;(SX18_20)
IFDEF SX48_52
		mov     w,#RD_latch         	;Initialize RD data latch
		mov     rd,w			
		mov     w,#RE_latch         	;Initialize RE data latch
		mov     re,w			
ENDIF	;(SX48_52)


	;------------------------------------------------------------------------------
	; Clear all Data RAM locations
	;------------------------------------------------------------------------------

zeroRam
IFDEF SX48_52   				;SX48/52 RAM clear routine
		mov	w,#$0a			;reset all ram starting at $0A
		mov	fsr,w
:zeroRam	clr	indf			;clear using indirect addressing
		incsz	fsr			;repeat until done
		jmp	:zeroRam

		_bank	bank0			;clear bank 0 registers
		clr	$10
		clr	$11
		clr	$12
		clr	$13
		clr	$14
		clr	$15
		clr	$16
		clr	$17
		clr	$18
		clr	$19
		clr	$1a
		clr	$1b
		clr	$1c
		clr	$1d
		clr	$1e
		clr	$1f

ELSE	;(SX48_52)				;SX18/20/28 RAM clear routine
		clr	fsr			;reset all ram banks
:zeroRam	sb	fsr.4			;are we on low half of bank?
		setb	fsr.3			;If so, don't touch regs 0-7
		clr	indf			;clear using indirect addressing
		incsz	fsr			;repeat until done
		jmp	:zeroRam
ENDIF	;(SX48_52)
	;------------------------------------------------------------------------------
	; Initialize program/VP registers
	;------------------------------------------------------------------------------
;VP_BEGIN: SPI Slave
		page	spisInit
		call	spisInit
;VP_END: SPI Slave
	;------------------------------------------------------------------------------
	; Setup and enable RTCC interrupt, WREG register, RTCC/WDT prescaler
	;------------------------------------------------------------------------------

	;?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?
	; Virtual Peripheral Guidelines Tip:
	;
	;	The suggested default values for the option register are:
	;	- Bit 7 set to 0: location $01 addresses the W register (WREG)
	;	- Bit 3 set to 1: Prescaler assigned to WatchDog Timer
	;
	;	If a routine must change the value of the option register (for example, to access
	;	the RTCC register directly), then it should restore the default value for the 
	;	option register before exiting.
	;
	;?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?!?


RTCC_ON		=	%10000000	;Enables RTCC at address $01 (RTW hi)
					;*WREG at address $01 (RTW lo) by default
RTCC_ID		=	%01000000	;Disables RTCC edge interrupt (RTE_IE hi)
					;*RTCC edge interrupt (RTE_IE lo) enabled by default
RTCC_INC_EXT	=	%00100000	;Sets RTCC increment on RTCC pin transition (RTS hi)
					;*RTCC increment on internal instruction (RTS lo) is default
RTCC_FE		=	%00010000	;Sets RTCC to increment on falling edge (RTE_ES hi)
					;*RTCC to increment on rising edge (RTE_ES lo) is default
RTCC_PS_ON	=	%00000000	;Assigns prescaler to RTCC (PSA lo)
RTCC_PS_OFF	=	%00001000	;Assigns prescaler to WDT (PSA hi)
PS_000		=	%00000000	;RTCC = 1:2, WDT = 1:1
PS_001		=	%00000001	;RTCC = 1:4, WDT = 1:2
PS_010		=	%00000010	;RTCC = 1:8, WDT = 1:4
PS_011		=	%00000011	;RTCC = 1:16, WDT = 1:8
PS_100		=	%00000100	;RTCC = 1:32, WDT = 1:16
PS_101		=	%00000101	;RTCC = 1:64, WDT = 1:32
PS_110		=	%00000110	;RTCC = 1:128, WDT = 1:64
PS_111		=	%00000111	;RTCC = 1:256, WDT = 1:128

OPTIONSETUP	equ	RTCC_PS_OFF|PS_111	; the default option setup for this program.
		mov	w,#OPTIONSETUP		; setup option register for RTCC interrupts enabled 
		mov	!option,w		; and no prescaler.
		jmp	@mainLoop

;------------------------------------------------------------------------------
; MAIN PROGRAM CODE 
;------------------------------------------------------------------------------


mainLoop

;VP_BEGIN SPI Demo
IFDEF	DEMO	

spisIdle
		snb	spisCSPin		; check for chip select
		jmp	spisIdle		; if not set, no action

		_bank	spisBank
		mov	w,spisStatus
		mov	spisOutPort,w		; Display status register with LEDs

		call	@spisGetByte		; Checks if received byte is available and returns byte, otherwise block 
		mov	localTemp0,w		; temporary store received byte/command
		and	w,#SPIM_VALID_CMD	; check if is a valid command
		sb	z			; if zero it is valid
		jmp 	spisIdle		; else it is invalid
	
		mov	w,localTemp0		; restore received valid command

		add	pc,w			; execute command
		jmp	spisIdle		;0 ; no action
		jmp	spisWrSr		;1 ; master write status register
		jmp	spisWrite		;2 ; master write
		jmp	spisRead		;3 ; master read
		jmp	spisWrDi		;4 ; reset write enable flag in status register
		jmp	spisRdSr		;5 ; master read status register
		jmp	spisWrEn		;6 ; set write enable on slave
		jmp	spisIdle		;7 ; return to Idle in main


;------------------------------------------------------------------------------
spisWrSr
;	Description:
; 		When a "write statusregister" command is sent to the slave this
;		routine receives the new status register content (1 byte).
;	Global Ram Destroyed:
;		
;	Inputs:	spisStatWEL
;	Output:	spisStatus
;------------------------------------------------------------------------------
		_bank	spisBank
		call	@spisGetByte		; waits until byte is ready and returns 
		snb	spisStatWEL		; check if WriteEnable is set...
		mov	spisStatus,w		; ... before writing byte to statusregister
		jmp	spisIdle		; return to Idle in main
;------------------------------------------------------------------------------
spisWrite
;	Description:
; 		When a "write" command is sent to the slave this routine 
;		receives address (16bit) and then the data to be written to the
;		slave seqentially until address extends $0F or CS=1.
;	Global Ram Destroyed:
;		localTemp0, fsr, 
;	Inputs:	spisCSPin, spisAddr, 
;	Output:	spisAddress, spisRamBank,
;------------------------------------------------------------------------------
		_bank	spisBank
		sb	spisStatWEL
		jmp	:exit

		call	@spisGetByte		; MSB of address
		mov	spisAddr+1,w		; store address
		sb	z
		jmp	:exit			; If MSB is not 0, then it is out of range

		call	@spisGetByte		; get LSB of address
		mov	spisAddr,w		; store LSB
		and	w,#SPIM_RANGE		; check if LSB of Addr is < SPIM_RANGE.
		sb	z
		jmp	:exit			; if not, exit

:again		call	@spisGetByte 
		mov	localTemp0,w		; temp. storage of received byte
		
		mov	w,#spisRamBank
		add	w,spisAddr		; w=address in RAM to write to
		mov	fsr,w			; 
		mov	w,localTemp0		; received byte to write/store
		mov	indf,w			; store received byte in RAM

		_bank	spisBank	
		mov	w,#1
		add	spisAddr,w		; increment RAM address pointer
		snb	dc			; check for carry from low nibble
		jmp	:exit			; done reading page

		sb	spisCSPin		; if CS=0 then continue transmitting
		jmp	:again

:exit		sb	spisCSPin		; CS=1 before leaving...
		jmp	:exit

		jmp	spisIdle		; return to Idle in main		
;------------------------------------------------------------------------------
spisRead
;	Description:
; 		When a "read" command is sent to the slave this routine 
;		receives the address to read from and then clocks the corresponding
;		data out on the SdoPin.
;	Global Ram Destroyed:
;		fsr
;	Inputs:	spisCSPin, spisAddr,
;	Output:	spisAddr, spisRamBank,
;------------------------------------------------------------------------------
		_bank	spisBank
		call	@spisGetByte		; MSB of address
		mov	spisAddr+1,w	
		sb	z
		jmp	:exit			; If MSB is not 0, then it is out of range
		call	@spisGetByte		; get LSB of address
		mov	spisAddr,w		; store LSB
		and	w,#SPIM_RANGE		; check if LSB of Addr is < SPIM_RANGE.
		sb	z
		jmp	:exit			; if not, exit
		
:again		mov	w,#spisRamBank
		add	w,spisAddr		; w=address in RAM to read from
		mov	fsr,w
		mov	w,indf			; byte to transfer

		call	@spisTxByte

		mov	w,#1
		add	spisAddr,w		; increment RAM address pointer
		snb	dc			; check for carry from low nibble
		jmp	:exit			; done reading page

		call	@spisGetByte 

		sb	spisCSPin		; if CS=0 then continue transmitting
		jmp	:again

:exit		sb	spisCSPin		; CS=1 before leaving...
		jmp	:exit
		jmp	spisIdle		; return to Idle in main
;------------------------------------------------------------------------------
spisWrDi
;	Description:
; 		When a "write disable" command is sent to the slave this
;		routine resets the WriteEnable flag in the slave status register.
;	Global Ram Destroyed:
;		None
;	Inputs:	None
;	Output:	spisStatWEL is cleared
;------------------------------------------------------------------------------
		_bank	spisBank
		clrb	spisStatWEL		; Reset WriteEnableLatch
		jmp	spisIdle		; return to Idle in main

;------------------------------------------------------------------------------
spisRdSr
;	Description:
; 		When a "read statusregister" command is sent to the slave this
;		routine clocks the contents of the slave status register out
;		on the SdoPin.
;	Global Ram Destroyed:
;		None
;	Inputs:	None
;	Output:	spisStatus (to SdoPin)
;------------------------------------------------------------------------------
		_bank	spisBank		; Read Status Register
		mov	w,spisStatus
		call	@spisTxByte		; Transmitt status byte
		jmp	spisIdle		; return to Idle in main
;------------------------------------------------------------------------------
spisWrEn
;	Description:
; 		When a "write enable" command is sent to the slave this
;		routine sets the write enable flag in the status register.
;	Global Ram Destroyed:
;		None
;	Inputs:	None
;	Output:	spisStatWEL is set.
;------------------------------------------------------------------------------
		_bank	spisBank
		setb	spisStatWEL		; Set WriteEnableLatch
		jmp	spisIdle		; return to Idle in main

ENDIF
;VP_END: SPI Demo
	jmp	mainLoop





;*****************************************************************************************
END		;End of program code
;*****************************************************************************************
